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K6T4008V1C, K6T4008U1C Family
Document Title
512Kx8 bit Low Power and Low Voltage CMOS Static RAM
CMOS SRAM
Revision History
Revision No. History
0.0 0.1 Initial Draft Revisied - Speed bin change KM68U4000C : 85/100ns 70/85/100ns - DC Characteristics change ICC : 5mA at read/write 4mA at read ICC1 : 3mA 4mA ICC2 : 35mA 30mA ISB : 0.5mA 0.3mA ISB1 : 10A 15A for commercial parts - Add 32-TSOP1-0820 Errata correct - 32-TSOP1-0813 products: T TG Finalize
Draft Data
January 13, 1998 June 12, 1998
Remark
Advance Preliminary
0.11
November 7, 1998
1.0
January 15, 1999
Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
1
Revision 1.0 January 1999
K6T4008V1C, K6T4008U1C Family
512Kx8 bit Low Power and Low Voltage CMOS Static RAM
FEATURES
* Process Technology: TFT * Organization: 512Kx8 * Power Supply Voltage K6T4008V1C Family: 3.0~3.6V K6T4008U1C Family: 2.7~3.3V * Low Data Retention Voltage: 2V(Min) * Three state output and TTL Compatible * Package Type: 32-SOP-525, 32-TSOP2-400F/R 32-TSOP1-0820F, 32-TSOP1-0813.4F
CMOS SRAM
GENERAL DESCRIPTION
The K6T4008V1C and K6T4008U1C families are fabricated by SAMSUNGs advanced CMOS process technology. The families support various operating temperature range and have various package type for user flexibility of system design. The families also support low data retention voltage for battery back-up operation with low data retention current.
PRODUCT FAMILY
Power Dissipation Product Family K6T4008V1C-B K6T4008U1C-B K6T4008V1C-F K6T4008U1C-F
1. The paramerter is measured with 30pF test load.
Operating Temperature Vcc Range 3.0~3.6V 2.7~3.3V Industrial(-40~85C) 3.0~3.6V 2.7~3.3V
Speed 701)/85ns 701)/85/100ns 701)/85ns 701)/85/100ns
Standby (ISB1, Max) 15A
Operating (ICC2, Max)
PKG Type
Commercial(0~70C)
30mA 20A
32-SOP 32-TSOP2-F/R 32-TSOP1-F 32-sTSOP1-F
PIN DESCRIPTION
A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 A17 WE A13 A8 A9 A11 OE A10 CS I/O8 I/O7 I/O6 I/O5 I/O4 VCC A15 A17 WE A13 A8 A9 A11 OE A10 CS I/O8 I/O7 I/O6 I/O5 I/O4 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 VSS
FUNCTIONAL BLOCK DIAGRAM
Clk gen. Precharge circuit.
A0 A1 A4 A5 A6 A7 A12 A14 A16 A18
32-SOP 32-TSOP2 (Forward)
32-TSOP2 (Reverse)
7 8 9 10 11 12 13 14 15 16
Row select
Memory array 1024 rows 512x8 columns
I/O1 A11 A9 A8 A13 WE A17 A15 VCC A18 A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CS I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2 A3 I/O8
Data cont
I/O Circuit Column select
32-TSOP1 32-STSOP1 (Forward)
Data cont
A2 A3 A8 A9 A10 A11 A13 A15 A17
CS WE
Control logic
Name
Function
Name Vcc Vss
Function Power Ground
OE
A0~A18 Address Inputs WE CS OE Write Enable Input Chip Select Input Output Enable Input
I/O1~I/O8 Data Inputs/Outputs
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. 2
Revision 1.0 January 1999
K6T4008V1C, K6T4008U1C Family
PRODUCT LIST
Commercial Temp Products(0~70C) Part Name K6T4008V1C-GB70 K6T4008V1C-GB85 K6T4008V1C-VB70 K6T4008V1C-VB85 K6T4008V1C-MB70 K6T4008V1C-MB85 K6T4008V1C-TB70 K6T4008V1C-TB85 K6T4008V1C-YB70 K6T4008V1C-YB85 K6T4008U1C-GB70 K6T4008U1C-GB85 K6T4008U1C-GB10 K6T4008U1C-VB70 K6T4008U1C-VB85 K6T4008U1C-VB10 K6T4008U1C-MB70 K6T4008U1C-MB85 K6T4008U1C-MB10 K6T4008U1C-TB70 K6T4008U1C-TB85 K6T4008U1C-TB10 K6T4008U1C-YB70 K6T4008U1C-YB85 K6T4008U1C-YB10 Function 32-SOP, 70ns, 3.3V, LL 32-SOP, 85ns, 3.3V, LL 32-TSOP2-F, 70ns, 3.3V, LL 32-TSOP2-F, 85ns, 3.3V, LL 32-TSOP2-R, 70ns, 3.3V, LL 32-TSOP2-R, 85ns, 3.3V, LL 32-TSOP1-F, 70ns, 3.3V, LL 32-TSOP1-F, 85ns, 3.3V, LL 32-sTSOP1-F, 70ns, 3.3V, LL 32-sTSOP1-F, 85ns, 3.3V, LL 32-SOP, 70ns, 3.0V, LL 32-SOP, 85ns, 3.0V, LL 32-SOP, 100ns, 3.0V, LL 32-TSOP2-F, 70ns, 3.0V, LL 32-TSOP2-F, 85ns, 3.0V, LL 32-TSOP2-F, 100ns, 3.0V, LL 32-TSOP2-R, 70ns, 3.0V, LL 32-TSOP2-R, 85ns, 3.0V, LL 32-TSOP2-R, 100ns, 3.0V, LL 32-TSOP1-F, 70ns, 3.0V, LL 32-TSOP1-F, 85ns, 3.0V, LL 32-TSOP1-F, 100ns, 3.0V, LL 32-sTSOP1-F, 70ns, 3.0V, LL 32-sTSOP1-F, 85ns, 3.0V, LL 32-sTSOP1-F, 100ns, 3.0V, LL
CMOS SRAM
Industrial Temp Products(-40~85C) Part Name Function 32-SOP, 70ns, 3.3V, LL 32-SOP, 85ns, 3.3V, LL 32-TSOP2-F, 70ns, 3.3V, LL 32-TSOP2-F, 85ns, 3.3V, LL 32-TSOP2-R, 70ns, 3.3V, LL 32-TSOP2-R, 85ns, 3.3V, LL 32-TSOP1-F, 70ns, 3.3V, LL 32-TSOP1-F, 85ns, 3.3V, LL 32-sTSOP1-F, 70ns, 3.3V, LL 32-sTSOP1-F, 85ns, 3.3V, LL 32-SOP, 70ns, 3.0V, LL 32-SOP, 85ns, 3.0V, LL 32-SOP, 100ns, 3.0V, LL 32-TSOP2-F, 70ns, 3.0V, LL 32-TSOP2-F, 85ns, 3.0V, LL 32-TSOP2-F, 100ns, 3.0V, LL 32-TSOP2-R, 70ns, 3.0V, LL 32-TSOP2-R, 85ns, 3.0V, LL 32-TSOP2-R, 100ns, 3.0V, LL 32-TSOP1-F, 70ns, 3.0V, LL 32-TSOP1-F, 85ns, 3.0V, LL 32-TSOP1-F, 100ns, 3.0V, LL 32-sTSOP1-F, 70ns, 3.0V, LL 32-sTSOP1-F, 85ns, 3.0V, LL 32-sTSOP1-F, 100ns, 3.0V, LL
K6T4008V1C-GF70 K6T4008V1C-GF85 K6T4008V1C-VF70 K6T4008V1C-VF85 K6T4008V1C-MF70 K6T4008V1C-MF85 K6T4008V1C-TF70 K6T4008V1C-TF85 K6T4008V1C-YF70 K6T4008V1C-YF85 K6T4008U1C-GF70 K6T4008U1C-GF85 K6T4008U1C-GF10 K6T4008U1C-VF70 K6T4008U1C-VF85 K6T4008U1C-VF10 K6T4008U1C-MF70 K6T4008U1C-MF85 K6T4008U1C-MF10 K6T4008U1C-TF70 K6T4008U1C-TF85 K6T4008U1C-TF10 K6T4008U1C-YF70 K6T4008U1C-YF85 K6T4008U1C-YF10
FUNCTIONAL DESCRIPTION
CS H L L L OE X
1)
WE X
1)
I/O High-Z High-Z Dout Din
Mode Deselected Output Disabled Read Write
Power Standby Active Active Active
H L X1)
H H L
1. X means dont care (Must be in low or high state)
ABSOLUTE MAXIMUM RATINGS1)
Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Operating Temperature Symbol VIN,VOUT VCC PD TSTG TA Ratings -0.5 to VCC+0.5 -0.3 to 4.6 1.0 -65 to 150 0 to 70 -40 to 85 Unit V V W C C C Remark K6T4008V1C-L, K6T4008U1C-L K6T4008V1C-P, K6T4008U1C-P
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
3
Revision 1.0 January 1999
K6T4008V1C, K6T4008U1C Family
RECOMMENDED DC OPERATING CONDITIONS1)
Item Supply voltage Ground Input high voltage Input low voltage Symbol Vcc Vss VIH VIL Product K6T4008V1C Family K6T4008U1C Family All Family K6T4008V1C, K6T4008U1C Family K6T4008V1C, K6T4008U1C Family Min 3.0 2.7 0 2.2 -0.3
3)
CMOS SRAM
Typ 3.3 3.0 0 Max 3.6 3.3 0 Vcc+0.32) 0.6 Unit V V V V
Note: 1. Commercial Product : TA=0 to 70C, otherwise specified Industrial Product : TA=-40 to 85C, otherwise specified 2. Overshoot : VCC+2.0V in case of pulse width 30ns 3. Undershoot : -2.0V in case of pulse width 30ns 4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1) (f=1MHz, TA=25C)
Item Input capacitance Input/Output capacitance
1. Capacitance is sampled, not 100% tested
Symbol CIN CIO
Test Condition VIN=0V VIO=0V
Min -
Max 8 10
Unit pF pF
DC AND OPERATING CHARACTERISTICS
Item Input leakage current Output leakage current Operating power supply current Average operating current Output low voltage Output high voltage Standby Current(TTL) Standby Current (CMOS)
1. Industrial product = 20A
Symbol ILI ILO ICC ICC1 ICC2 VOL VOH ISB ISB1 VIN=Vss to Vcc
Test Conditions
Min -1 -1 2.2 -
Typ -
Max 1 1 4 4 30 0.4 0.3 151)
Unit A A mA mA mA V V mA A
CS=VIH or OE=VIH or WE=VIL VIO=Vss to Vcc IIO=0mA, CS=VIL, VIN=VIL or VIH, Read
Cycle time=1s, 100% duty, IIO=0mA CS0.2V,VIN0.2V or VINVcc-0.2V
Cycle time=Min, 100% duty, IIO=0mA, CS=VIL, VIN=VIH or VIL
IOL=2.1mA IOH=-1.0mA CS=VIH, Other inputs = VIL or VIH CSVcc-0.2V, Other inputs=0~Vcc
4
Revision 1.0 January 1999
K6T4008V1C, K6T4008U1C Family
AC OPERATING CONDITIONS
TEST CONDITIONS(Test Load and Input/Output Reference)
Input pulse level: 0.4 to 2.2V Input rising and falling time: 5ns Input and output reference voltage:1.5V Output load(see right): CL=100pF+1TTL CL1)=30pF+1TTL
1. 70ns product
CMOS SRAM
CL1) 1. Including scope and jig capacitance
AC CHARACTERISTICS (K6T4008V1C Family: Vcc=3.0~3.6V, K6T4008U1C Family: Vcc=2.7~3.3V
Commercial product:: TA=0 to 70C, Industrial product: TA=-40 to 85C) Speed Bins Parameter List Symbol 70ns Min Read cycle time Address access time Chip select to output Output enable to valid output Read Chip select to low-Z output Output enable to low-Z output Chip disable to high-Z output Output disable to high-Z output Output hold from address change Write cycle time Chip select to end of write Address set-up time Address valid to end of write Write Write pulse width Write recovery time Write to output high-Z Data to write time overlap Data hold from write time End write to output low-Z tRC tAA tCO tOE tLZ tOLZ tHZ tOHZ tOH tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOW 70 10 5 0 0 10 70 60 0 60 55 0 0 30 0 5 Max 70 70 35 25 25 25 Min 85 10 5 0 0 10 85 70 0 70 55 0 0 35 0 5 85ns Max 85 85 40 25 25 25 100ns Min 100 10 5 0 0 15 100 80 0 80 70 0 0 40 0 5 Max 100 100 50 30 30 30 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Units
DATA RETENTION CHARACTERISTICS
Item Vcc for data retention Data retention current Data retention set-up time Recovery time
1. Industrial product = 20A
Symbol VDR IDR tSDR tRDR
Test Condition CSVcc-0.2V Vcc=3.0V, CSVcc-0.2V See data retention waveform
Min 2.0 0 5
Typ 0.5 -
Max 3.6 15 1)
Unit V A ms
5
Revision 1.0 January 1999
K6T4008V1C, K6T4008U1C Family
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)
tRC Address tOH Data Out Previous Data Valid tAA
CMOS SRAM
Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC Address tAA tCO1 CS tOE OE tOLZ tLZ Data Valid tOHZ tHZ tOH
Data out
NOTES (READ CYCLE)
High-Z
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection.
6
Revision 1.0 January 1999
K6T4008V1C, K6T4008U1C Family
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC Address tCW(2) CS tAW tWP(1) WE tAS(3) Data in tWHZ Data out Data Undefined tDW Data Valid tOW tDH tWR(4)
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(2) (CS
Controlled)
tWC Address tAS(3) CS tAW tWP(1) WE tDW Data in Data Valid tDH tCW(2) tWR(4)
Data out
NOTES (WRITE CYCLE)
High-Z
High-Z
1. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going Low and WE going low : A write end at the earliest transition among CS going high and WE going high, tWP is measured from the begining of write to the end of write. 2. tCW is measured from the CS going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
DATA RETENTION WAVE FORM
CS controlled
VCC 3.0/2.7V tSDR Data Retention Mode tRDR
2.2V VDR CSVCC - 0.2V CS GND
7
Revision 1.0 January 1999
K6T4008V1C, K6T4008U1C Family
PACKAGE DIMENSIONS
32 PIN PLASTIC SMALL OUTLINE PACKAGE (525mil)
CMOS SRAM
Units: millimeters(inches)
0~8 #32 #17
14.120.30 0.5560.012
11.430.20 0.4500.008
13.34 0.525
#1 20.87 0.822 MAX 20.470.20 0.8060.008
#16 2.740.20 0.1080.008 3.00 0.118 MAX
0.20 +0.10 -0.05 0.008+0.004 -0.002
0.800.20 0.0310.008
0.10 MAX 0.004 MAX
+0.100 -0.050 +0.004 0.016 -0.002
( 0.71 ) 0.028
0.41
1.27 0.050
0.05 MIN 0.002
8
Revision 1.0 January 1999
K6T4008V1C, K6T4008U1C Family
PACKAGE DIMENSIONS
32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0820F)
CMOS SRAM
Units: millimeters(inches)
0.20
+0.10 -0.05 +0.004 0.008 -0.002
20.000.20 0.7870.008 #32 ( 8.00 0.315 0.25 ) 0.010
#1
8.40 0.331MAX
0.50 0.0197
#16
#17 1.000.10 0.0390.004 1.20 0.047MAX 0.15
+0.10 -0.05 +0.004 0.006 -0.002
0.05 0.002 MIN
0.25 0.010 TYP
18.400.10 0.7240.004
0~8
0.45 ~0.75 0.018 ~0.030
(
0.50 ) 0.020
32 PIN SMALLER THIN SMALL OUTLINE PACKAGE TYPE I (0813.4F)
0.20
+0.10 -0.05 0.008+0.004 -0.002
13.400.10 0.5280.008 #32 ( 8.40 0.331 MAX 8.00 0.315 0.25 ) 0.010
#1
0.50 0.0197
#16
#17 1.000.10 0.0390.004 1.20 0.047 MAX 11.800.10 0.4650.004
+0.10 -0.05 0.006+0.004 -0.002
0.25 0.010 TYP
0.15
0~8
0.45 ~0.75 0.018 ~0.030
(
0.50 ) 0.020
9
1.10 MAX 0.004 MAX
0.10 MAX 0.004MAX 0.05 0.002 MIN
Revision 1.0 January 1999
K6T4008V1C, K6T4008U1C Family
PACKAGE DIMENSIONS
32 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F)
0.25 ( 0.010 ) #32 #17
CMOS SRAM
Units: millimeters(inches)
0~8
0.45~0.75 0.018 ~ 0.030
11.760.20 0.4630.008
#1 21.35 0.841 MAX 20.950.10 0.8250.004
#16 1.000.10 0.0390.004 1.20 0.047 MAX 0.15 +0.10 -0.05 0.006 +0.004 -0.002
10.16 0.400
(
0.50 ) 0.020
0.10 MAX 0.004 MAX
( 0.95 ) 0.037
0.400.10 0.0160.004
1.27 0.050
0.05 MIN 0.002
32 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400R)
0.25 ( ) 0.010 #1 #16
0~8
0.45 ~0.75 0.018 ~ 0.030
11.760.20 0.4630.008
#32 21.35 0.841 MAX 20.950.10 0.8250.004
#17 1.000.10 0.0390.004 1.20 0.047 MAX 0.10 MAX 0.004 MAX
+0.10 -0.05 0.006 +0.004 -0.002
10.16 0.400
0.15
( 0.50 ) 0.020
(
0.95 ) 0.037
0.400.10 0.0160.004
1.27 0.050
0.05 MIN 0.002
10
Revision 1.0 January 1999

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